commit - 06470645cac3260a904d9ef8316c94143054bbab
commit + 0d6ca1e880abde21d60fbe69b4fb6cca1f7b8fae
blob - 67501a09189ce4ffa3e0898056ecdd97ff27c118
blob + 957cdf9ebd7179c303641dd36299671837fb8f52
--- src/chip8.rs
+++ src/chip8.rs
@@ -48,6 +48,7 @@ impl Chip8 {
         let nnn = instruction & 0x0FFF;
         let kk = (instruction & 0x00FF) as u8;
         let x = (instruction & 0x0F00) >> 8;
+        let y = (instruction & 0x00F0) >> 4;
 
         match instruction & 0xF000 {
             0x0 => match nnn {
@@ -78,24 +79,33 @@ impl Chip8 {
                 self.stack.push(self.pc + 2);
                 self.pc = nnn;
             },
-            // SE
+            // SE Vx, byte
             0x3 => {
-                // skip next instruction if Vx == kk
+                // skip next instruction if Vx == byte
                 if self.regs[x as usize] == kk {
                     self.pc += 4;
                 } else {
                     self.pc += 2;
                 }
             },
-            // SNE
+            // SNE Vx, byte
             0x4 => {
-                // skip next instruction if Vk != kk
+                // skip next instruction if Vx != byte
                 if self.regs[x as usize] != kk {
                     self.pc += 4;
                 } else {
                     self.pc += 2;
                 }
             },
+            // SE Vx, Vy
+            0x5 => {
+                // skip next instruction if Vx == Vy
+                if self.regs[x as usize] == self.regs[y as usize] {
+                    self.pc += 4;
+                } else {
+                    self.pc += 2;
+                }
+            },
             _ => {
                 return Err(format!("{:#06x}: not an instruction", instruction));
             }