commit - 0d6ca1e880abde21d60fbe69b4fb6cca1f7b8fae
commit + 7a1da51f6f97b298b9e252a0bcccff3b28805636
blob - 957cdf9ebd7179c303641dd36299671837fb8f52
blob + 10b95dc48d8bb1ecddc9f258daf2e18207c1d479
--- src/chip8.rs
+++ src/chip8.rs
@@ -106,6 +106,16 @@ impl Chip8 {
                     self.pc += 2;
                 }
             },
+            // LD
+            0x6 => {
+                // save kk into Vx
+                self.regs[x as usize] = kk;
+            },
+            // ADD
+            0x7 => {
+                // set Vx to Vx + kk
+                self.regs[x as usize] += kk;
+            },
             _ => {
                 return Err(format!("{:#06x}: not an instruction", instruction));
             }