commit dce524c1691c419987ce7a2f2e66a62ddc001baa
from: Witcher01 <witcher01+github@posteo.net>
date: Sun Aug  1 18:26:39 2021 UTC

added the rest of the instructions (not all are implemented)

commit - 8660646dc4d56e97f36595433b5c5737b8fcedb4
commit + dce524c1691c419987ce7a2f2e66a62ddc001baa
blob - 35c59a95ec3cee8cddcdd4ba4961965c42e94354
blob + 848f965fe67bc42ac325d9006879eb30dbf16d3f
--- Cargo.lock
+++ Cargo.lock
@@ -883,4 +883,5 @@ name = "yac8e"
 version = "0.1.0"
 dependencies = [
  "minifb",
+ "rand",
 ]
blob - 9f75a428b8abfcd21982ba3643b9e0f65dd99f42
blob + 62e48ced1ae8c3d18648eb81e43ee29357a7152d
--- Cargo.toml
+++ Cargo.toml
@@ -7,3 +7,4 @@ edition = "2018"
 
 [dependencies]
 minifb = "0.19"
+rand = "0.8.0"
blob - f8cdd4f86eb97f48254ef798d678cffcc6b3f0c3
blob + 73c156a165dbc903619e86f9800ed545d49423c3
--- src/chip8.rs
+++ src/chip8.rs
@@ -49,8 +49,8 @@ impl Chip8 {
         let kk = (instruction & 0x00FF) as u8;
         let x = ((instruction & 0x0F00) >> 8) as usize;
         let y = ((instruction & 0x00F0) >> 4) as usize;
-        // "least significant hex"
-        let lsh = instruction & 0x000F;
+        // least significant nibble
+        let lsn = instruction & 0x000F;
 
         match (instruction & 0xF000) >> 12 {
             0x0 => match nnn {
@@ -119,7 +119,7 @@ impl Chip8 {
                 self.regs[x] += kk;
             },
             0x8 => {
-                match lsh {
+                match lsn {
                     // LD Vx, Vy
                     0x0 => {
                         self.regs[x] = self.regs[y];
@@ -181,7 +181,7 @@ impl Chip8 {
             },
             // SNE Vx, Vy
             0x9 => {
-                if lsh != 0 {
+                if lsn != 0 {
                     return Err(format!("{:#06x}: not an instruction", instruction));
                 }
 
@@ -191,6 +191,89 @@ impl Chip8 {
                     self.pc += 2;
                 }
             },
+            // LD I, addr
+            0xA => {
+                self.i_reg = nnn;
+                self.pc += 2;
+            },
+            // JP V0, addr
+            0xB => {
+                self.pc = (self.regs[0x0] as u16) + nnn;
+            },
+            // RND Vx, byte
+            0xC => {
+                self.regs[x] = rand::random::<u8>() & kk;
+                self.pc += 2;
+            },
+            // DRW Vx, Vy, nibble
+            // TODO: implement
+            0xD => {
+                unimplemented!();
+            },
+            0xE => {
+                match instruction & 0x00FF {
+                    // SKP Vx
+                    // TODO: skip either 2 or 4 bytes
+                    0x9E => {
+                        unimplemented!();
+                    },
+                    // SKNP Vx
+                    // TODO: skip either 2 or 4 bytes
+                    0xA1 => {
+                        unimplemented!();
+                    },
+                    _ => {
+                        return Err(format!("{:#06x}: not an instruction", instruction));
+                    }
+                };
+            },
+            0xF => {
+                match instruction & 0x00FF {
+                    // LD Vx, DT
+                    0x07 => {
+                        unimplemented!();
+                    },
+                    // LD Vx, K
+                    0x0A => {
+                        unimplemented!();
+                    },
+                    // LD DT, Vx
+                    0x15 => {
+                        unimplemented!();
+                    },
+                    // LD ST, Vx
+                    0x18 => {
+                        unimplemented!();
+                    },
+                    // ADD I, Vx
+                    0x1E => {
+                        unimplemented!();
+                    },
+                    // LD F, Vx
+                    0x29 => {
+                        unimplemented!();
+                    },
+                    // LD B, Vx
+                    0x33 => {
+                        unimplemented!();
+                    },
+                    // LD [I], Vx
+                    0x55 => {
+                        unimplemented!();
+                    },
+                    // LD Vx, [I]
+                    0x65 => {
+                        unimplemented!();
+                    },
+                    _ => {
+                        return Err(format!("{:#06x}: not an instruction", instruction));
+                    }
+                };
+
+                // NOTE: unreachable because of everything above being unimplemented
+                // TODO: remove this note after implementing
+                self.pc += 2;
+            },
             _ => {
                 return Err(format!("{:#06x}: not an instruction", instruction));
             }